Method of making metallization and contact structures in an integrated circuit using a timed trench etch

ABSTRACT

The invention concerns a method for forming metallization and contact structures in an integrated circuit. The method involoves the steps of etching a trench in the trench dielectric layer a trench dielectric layer of a composite structure containing a semiconductor substrate comprising an active region, a gate structure thereover, and dielectric spacers adjacent to the gate structure, a contact dielectric layer; and the trench dielectric layer; etching the contact dielectric layer under conditions which do not damage the gate structure to form a first contact opening that exposes a region of the semiconductor substrate; and depositing a conductive material into the contact opening and the trench.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of formingmetallization and contact structures in an integrated circuit, using a“dual damascene”-like procedure.

[0003] 2. Discussion of the Background

[0004] During the preparation of integrated circuits, electricalconnections between active regions of a semiconductor device arenecessary.

[0005] One method of preparation involves the use of self-alignedcontact (SAC) technology, which may comprise forming an opening througha dielectric material to an active region of a semiconductor device,wherein a gate structure adjacent to the active region may be protectedduring the contact opening etching step by encapsulation with a materialwhich may have a lower etching rate than that of the surroundingdielectric material. In this fashion, one may reduce the total areaconsumed by functional circuitry while minimizing damage to the gatestructure that might otherwise result from small errors in aligning thecontact hole with the underlying conductive region.

[0006] After such an opening has been formed, it may be filled with aconductive material and planarized to form a self-aligned contact. Twoor more SACs may be electrically connected by a local trench which maybe formed by patterning a metal layer, such that the metal layerelectrically connects the SACs, followed by depositing and optionallyplanarizing a dielectric material.

[0007] A “damacene” metallization layer, is an alternative to thepattered metal layer described above. A “damacene” metal layer is onewhere a trench or trough is formed in a dielectric material layer, thenthe trench is filled with a conductive metal. Damascene processes arebecoming more widely used in semiconductor processing.

[0008] Problems observed in the interface between the SAC and theinterconnect formed by damascene metallization have produced “dualdamascene” processes, in which a channel is formed in a trenchdielectric and an opening is formed in an underlying contact dielectric,both of which are then filled with a metal. This technology offers theadvantages of simultaneously forming the contact and interconnect, whichcan result in reduced processing steps and a more highly conductiveinterface between the contact and interconnect structures.

[0009] Yen U.S. Pat. No. 5,861,676, reports a method of forminginterconnects and contacts between elements in a semiconductor orintegrated circuit.

[0010] Avanzino et al. U.S. Pat. No. 5,795,823 reports the fabricationof conductive lines and connecting vias using dual damascene with onlyone mask pattern. This is also reported by Avanzino et al. in U.S. Pat.No. 5,614,765.

[0011] Dai U.S. Pat. No. 5,877,076 reports a dual damascene processusing opposite type two-layered photoresist.

[0012] Dai et al U.S. Pat. No. 5,876,075 reports forming dual damascenepatterns using a single photoresist process.

[0013] Dai U.S. Pat. No. 5,882,996 discloses a method for patterningdual damascene interconnections using a developer soluble ARCinterstitial layer.

[0014] Huang et al. U.S. Pat. No. 5,635,423 reports a modified dualdamascene process in which an initial opening in a trench dielectric isenlarged while simultaneously extending a via opening through an etchstop layer and a via dielectric.

[0015] Qiao and Nulty U.S. Ser. No. 326,432, filed on Jun. 4, 1999report a method and structure for making self-aligned contacts.

[0016] Blosse et al. IEEE 1999 International Interconnect TechnologyConference, p 215-217 reports a comparison between counterbore dualdamascene and self-aligned dual damascene in forming aluminuminterconnects using PVD.

[0017] In spite of known techniques for forming contacts andinterconnects, increases in device density and demands for increasedprocessing efficiency, have spurred new efforts to effectively producesemiconductor interconnections.

SUMMARY OF THE INVENTION

[0018] One embodiment of the present invention involves a method ofpreparing interconnects and self-aligned contact structures using a dualdamascene process.

[0019] Another embodiment of the present invention, involves a dualdamacene method of forming metallization and self-aligned contactstructures to active regions of a semiconductor device controlled by agate structure.

[0020] Another embodiment of the present invention involves a dualdamacene method of forming metallization and contact structures to anactive region of a semiconductor device, controlled by a gate structure,in which the gate is protected during etching of the contact hole.

[0021] Another embodiment of the present invention, involves a dualdamacene method of forming metallization and contact structures to anactive region of a semiconductor device controlled by a gate structurein which the gate may be protected from etching during etching of thecontact hole and in which etching of the trench dielectric is timed andwhich may be stopped before substantial etching of the contactdielectric occurs.

[0022] Another embodiment of the present invention, involves a dualdamacene method of forming metallization and contact structures to anactive region of a semiconductor device controlled by a gate structurein which the gate may be protected from etching during etching of thecontact hole and in which etching of the contact hole through thecontact dielectric layer may be conducted in the absence of a patternedphotoresist.

[0023] These and other embodiments of the present invention are madepossible by a dual damascene method that simultaneously forms a metalinterconnect structure and one or more self-aligned contacts.

BRIEF DESCRIPTION OF THE DRAWINGS

[0024] A more complete appreciation of the invention and many of theattendant advantages thereof will be readily obtained as the samebecomes better understood by reference to the following detaileddescription when considered in connection with the accompanyingdrawings, wherein:

[0025]FIG. 1 illustrates a semiconductor structure comprising a contactdielectric layer, a trench dielectric layer and an anti-reflectivecoating layer;

[0026]FIG. 2 illustrates a semiconductor structure further comprising apatterned trench mask and an etched trench dielectric layer;

[0027]FIG. 3 illustrates a semiconductor structure comprising an etchedtrench dielectric layer;

[0028]FIG. 3(B) illustrates a semiconductor structure comprising anetched trench dielectric layer, anti-reflective coating layer and anetch stop layer overlying the gate structure;

[0029]FIG. 4 illustrates a semiconductor structure comprising an etchedtrench dielectric layer, and a patterned contact opening mask;

[0030]FIG. 4(A) illustrates a semiconductor structure comprising anetched trench dielectric layer, an anti-reflective coating layer and apatterned contact opening mask;

[0031]FIG. 4(B) illustrates a semiconductor structure comprising anetched trench dielectric layer, an anti-reflective coating layer and apatterned contact opening mask, in which the contact mask opening is notperfectly aligned with the etched trench;

[0032]FIG. 5 illustrates a top view of the semiconductor structureillustrated in FIG. 4;

[0033]FIG. 6 illustrates a semiconductor structure comprising a trenchand contact hole opening etched in the trench dielectric layer, wherethe trench dielectric layer functions as a hard mask for etching thecontact dielectric layer;

[0034]FIG. 7 illustrates a semiconductor structure comprising a trenchetched in the trench dielectric layer and a contact hole etched in thecontact dielectric layer;

[0035]FIG. 8 illustrates a semiconductor structure further comprising aliner layer and a continuous self-aligned contact and interconnectstructure;

[0036]FIG. 9 illustrates a semiconductor structure comprising acontinuous self-aligned contact and interconnect structure afterplanarization;

[0037]FIG. 10 illustrates a top view of the semiconductor structureillustrated in FIG. 9; and

[0038]FIG. 10(B) illustrates a top view of the semiconductor structureillustrated in FIG. 9, in which the contact opening is not perfectlyaligned with the trench.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0039] Within one context of the present invention, a multi-levelsubstrate comprising active regions and dielectric layers is etched toform both a trench and contact hole in which alignment of the contacthole mask is given processing latitudes using SAC techniques.

[0040] A multi-level substrate to be processed according to the presentinvention may be prepared according to conventional methods known tothose of ordinary skill in the art. Suitable substrates comprisingactive regions, gate structures and dielectric layers may be prepared byconventional methods known to those of ordinary skill in the art.

[0041] Non-limiting examples of active regions to which an opening maybe formed include a source or a drain region of a silicon, germanium orGaAs substrate (which may be lightly, heavily and/or very heavily dopedwith conventional N-dopants [such as nitrogen, phosphorous, arsenic,antimony, bismuth, tellurium, sulfur, mixtures thereof etc.] orP-dopants [such as B, Al, Ga, In, mixtures thereof, etc.]), silicidesource and drain regions, metallization or conductive (metal)interconnect structures, field oxide regions, gate and/or word linestructures (which may comprise [doped] polysilicon and/or a conventionalmetal silicide located in the first functional layer of a conductivematerial, above the substrate), etc.

[0042] Suitable gate structures, include those known to those ofordinary skill in the art, and which by way of example may comprise aMOS structure, a floating gate/control gate structure (e.g. for anon-volatile transistor), a SONOS transistor, etc.

[0043] Before depositing the contact dielectric, one may form spacers,which may prevent or inhibit etching of the gate or metallizationstructure while etching the contact hole, and which may protectconventional lightly doped source/drain structures during (source/drain)well implants. Suitable spacers may be formed by conventional methodsknown to those of ordinary skill in the art, such as depositing adielectric spacer material by LPCVD or PECVD, followed byanisotropically etching the dielectric spacer material to form thespacer. A suitable dielectric spacer material may be selected by thoseof ordinary skill in the art and may provide a lower rate of etchingrelative to the surrounding contact dielectric material. For example,one suitable spacer material comprises a nitride such as silicon nitride(e.g. when the contact dielectric comprises an oxide) or a silicon oxide(e.g. when the contact dielectric comprises a nitride or a secondcompositionally distinct oxide). Typically the spacer layer will have awidth, measured at the base, of from about 100 to about 1,500 Å,generally about 500 Å to 800 Å.

[0044] Within the context of the present invention it may also bedesirable for the etch rate of the contact dielectric material to differsufficiently from that of the gate structure (particularly the capdielectric) under the conditions for etching the contact opening toavoid substantial etching of the gate structure and/or cap dielectric.Thus, it is within the scope of the present invention to form aprotective cap dielectric layer over the gate from a material such assilicon nitride to increase the difference in etch rates between thecontact dielectric layer and the gate structure. The formation of a capdielectric and the selection of a suitable material is within the levelof ordinary skill in the art, and may be based on conventional SACtechniques.

[0045] Suitable contact dielectric materials are deposited over the gatestructure (and optionally planarized) by conventional methods known tothose of ordinary skill in the art. Suitable contact dielectricmaterials may be selected by those of ordinary skill in the art suchthat the etching rate of the contact dielectric is sufficiently greaterthan that of the dielectric spacer material surrounding the gatestructure under the conditions used to etch the contact dielectric topermit relatively complete etching of the contact dielectric materialwithout substantial etching of the dielectric spacer material (and/orwhile reliably protecting the gate 12 from the contact hole etchprocess). For example, the contact dielectric layer may comprise one ormore layers of dielectric materials such as silicon dioxide or a dopedsilicate glass such as fluorosilicate glass (FSG), borosilicate glass(BSG), phosphosilicate glass (PSG) and/or borophosphosilicate glass(BPSG). The contact dielectric material may be subject to a reflow stepfor densification and/or planarization after deposition. In addition,the contact dielectric material may be further planarized, for exampleby isotropic etching, annealing or chemical mechanical polishing (CMP),by processes known to those skilled in the art.

[0046] Further examples of contact dielectric materials includeconventional oxides, nitrides, oxynitrides, and other dielectrics, suchas spin-on glass (SOG), P-doped silicon oxide (P-glass), silicon nitride(Si_(x)N_(y)), silicon oxynitride (e.g., of the general formulaSi_(a)O_(x)N_(y)such that (x/2)+(3y/4)=a), Al₂O₃, metal nitrides such asaluminum nitride (e.g. AlN), V₂O₅, tetraethylorthosilicate-based oxides,titanium oxide, aluminum oxynitrides (e.g. of the general formulaAl_(b)O_(x)N_(y)such that (2x/3)+y=b), aluminosilicates and nitridesthereof (e.g. of the general formula [Si_(a)Al_(b)O_(x)N_(y)] wherex=2a+3b/2 and y=4a/3+b), and boron- and/or phosphorous-doped aluminatesand aluminosilicates. Preferably, the contact dielectric materialcomprises a layer of PSG containing an atomic % of P (relative to thesum of P atoms and Si atoms) of 1-15%, preferably 3-12%, more preferably5-11%.

[0047] The final thickness of the contact dielectric layer is notparticularly limited, but preferably is within the range of about 0.3 to3.0 μm, more preferably 0.4 to 2.0 μm, even more preferably 0.5 to 1.0μm. A typical value for a 0.18 μm gate width technology may be 0.6 μm.The contact dielectric layer may comprise a single dielectric materialor multiple layers of the same or different dielectric materials.

[0048] Overlying the contact dielectric is a trench dielectric materialof the same, or preferably greater, thickness as the interconnectstructure to be formed therein. Suitable trench dielectric materials mayexhibit a higher rate of etching than the underlying contact dielectricmaterial, under the conditions used to etch the trench dielectric.

[0049] Examples of trench dielectric materials include conventionaloxides, nitrides, oxynitrides, and other dielectrics, such asborophosphosilicate glass (BPSG), borosilicate glass (BSG),fluorosilicate glass, phosphosilicate glass, undoped silicate glass,spin-on glass (SOG), P-doped silicon oxide (P-glass), silicon nitride(Si_(x)N_(y)), silicon dioxide, silicon oxynitride (e.g. of the generalformula [Si_(a)O_(x)N_(y)] such that (x/2)+(3y/4)=a), Al₂O₃, metalnitrides such as aluminum nitride [e.g. AlN], Si₃N₄, V₂O₅,tetraethylorthosilicate-based oxides and titanium oxide, aluminumoxynitrides (e.g. of the general formula [Al_(b)O_(x)N_(y)] such that(2x/3)+y=b), aluminosilicates and nitrides thereof (e.g. of the generalformula [Si_(a)Al_(b)O_(x)N_(y)] where x=2a+3b/2 and y=4a3+b), boron-and/or phosphorous-doped aluminates and aluminosilicates. Preferably,the trench dielectric material is formed by plasma assisted vaporpyrolysis of TEOS (also known as tetraethylorthosilicate ortetraethoxysilane), which vapor may further include trimethylborate(TMB) as a boron source and/or phosphine as a phosphorus source, at apressure of from about 0.3 to about 1 torr and at a temperature ofapproximately 640-660° C.

[0050] The thickness of trench dielectric layer is not particularlylimited, but preferably is within the range of about 0.06 to 3.0 μm,more preferably 0.10 to 1.5 μm, even more preferably 0.15 to 1.0 μm. Fora process having a 0.18 μm gate width, the trench thickness may be about0.20 μm. The trench dielectric layer may comprise a single dielectricmaterial, however, it may also comprise multiple layers of the same ordifferent dielectric materials.

[0051] In FIG. 1, a semiconductor structure is illustrated, comprising(i) a contact dielectric layer 1 surrounding a gate structure 3 whichincludes gate 12, “cap” dielectric 13, and (optionally) spacers 2, (ii)an overlying trench dielectric layer 4 and (iii) an anti-reflectivecoating layer 14. An active region (not illustrated) may lie in thesubstrate but adjacent to the gate structure 3.

[0052] A trench may be formed in the trench dielectric layer of thesemiconductor structure by conventional photolithographic and etchingtechniques. However, to obtain greater resolution duringphotolithographic processing, an anti-reflective coating (ARC) layer 14may be deposited on the exposed surface of the trench dielectricmaterial prior to depositing a photoresist layer 5 for forming a trenchmask (see FIG. 2). One suitable ARC may comprise a bottomanti-reflective coating (BARC), which may be an organic material such asthose commercially available from Brewer Science (Rolla, Mo.), Clariant,Hitachi, or Tokyo Ohka (see for example, Singer, SemiconductorInternational March 1999, vol. 22 (3), pp. 55-59, the relevant portionsof which are hereby incorporated by reference). Alternatively, aninorganic dielectric layer such as a dielectric ARC layer (e.g.,SiO_(x)N_(y), or DARC™, available from Applied Materials, Santa Clara,Calif.), a sacrificial ARC layer (e.g TiN) or a multilayered structurecomprising the previously mentioned ARC layer materials, may beemployed. The dielectric ARC layer may be of a thickness of from about200 Å to about 1,000 Å, typically 300 Å to 700 Å.

[0053] A photoresist layer for patterning the trench dielectric may beformed on the trench dielectric or ARC layer by conventional methodsknown to those of ordinary skill in the art, such as by spin coating.The resist material may then be conventionally patterned.

[0054] Negative resist materials may contain chemically inert polymercomponents such as rubber and/or photoreactive agents that react withlight to form cross-links, e.g. with the rubber. When placed in anorganic developer solvent, the unexposed and unpolymerized resistdissolves, leaving a polymeric pattern in the exposed regions. Thepreparation and deposition of negative resist materials is within thelevel of skill of one of ordinary skill in the art and can be performedwithout undue experimentation. Specific non-limiting examples ofnegative resist systems include cresol epoxy novolac-based negativeresists, as well as negative resists containing one or morephotoreactive polymers as described in Kirk-Othmer Encyclopedia ofChemical Technology, 3rd Edition, vol 17, entitled “PhotoreactivePolymers”, pages 680-708, the relevant portions of which are herebyincorporated by references.

[0055] Positive resists have photoreactive components that are destroyedin the regions exposed to light. Typically the resist is removed in anaqueous alkaline solution, where the exposed region dissolves away. Thepreparation and deposition of positive resist materials is within thelevel of skill of one of ordinary skill in the art and can be performedwithout undue experimentation. Specific non-limiting examples ofsuitable positive resist systems include Shipley XP9402, JSR KRK-K2G andJSR KRF-L7 positive resists, as well as positive resists containing oneor more photoreactive polymers as described in Kirk-Othmer Encyclopediaof Chemical Technology, 3rd Edition, vol. 17, entitled “PhotoreactivePolymers”, pages 680-708, the relevant portions of which are herebyincorporated by references.

[0056] Examples of resist materials are also described by Baver et al,IBM Tech. Discl. Bull (USA) Vol. 22, No. 5 Oct. 1979, pp 1855; Tabei,U.S. Pat. No. 4,613,404; Taylor et al, J. Vac. Sci. Technol. B. Vol. 13,No. 6, 1995, pp 3078-3081; Argitis et al, J. Vac. Sci. Technol. B. Vol.13, No. 6, 1995, pp 3030-3034; Itani et al, J. Vac. Sci. Technol. B.Vol. 13, No. 6, 1995 pp 3026-3029; Ohfuji et al, J. Vac. Sci. Technol.B. Vol. 13, No. 6, 1995 pp 3022-3025; Trichkov et al, J. Vac. Sci.Technol. B. Vol. 13, No. 6, 1995, pp 2986-2993; Capodieci et al, J. Vac.Sci. Technol. B. Vol. 13, No. 6, 1995, pp 2963-2967; Zuniga et al, J.Vac. Sci. Technol. B. Vol. 13, No. 6, 1995, pp 2957-2962; Xiao et al, J.Vac. Sci. Technol. B. Vol. 13, No. 6, 1995, pp 2897-2903; Tan et al J.Vac. Sci. Technol. B. Vol. 13, No. 6, 1995, pp 2539-2544; and Mavone etal J. Vac. Sci. Technol. Vol. 12, No. 6, 1995, pp 1382-1382. Therelevant portions of the above-identified references that describe thepreparation and deposition of resist materials is hereby incorporated byreference. Selection of a resist material for the particular etchingconditions is within the level of skill of one of ordinary skill in theart and can be performed without undue experimentation.

[0057] The photoresist layer may be patterned by conventionallithography steps known to those of ordinary skill in the art, such asby exposing the photoresist layer to radiation passed through aphotolithography mask. Such selective exposure, followed by conventionaldeveloping, can produce a trench pattern, corresponding to the wiringpattern of a metallization structure. Depending on the type ofphotoresist material (i.e., positive or negative), selected portions ofthe photoresist material can be removed by developing with a suitabledeveloper/solvent, and the resulting pattern may be heated (e.g., bybaking in a furnace) prior to subsequent etching.

[0058] A photoresist is deposited and patterned to form a trench (orlocal interconnect) mask 5 as illustrated in FIG. 2. The exposed ARClayer 14 and trench dielectric material layer 4 may be etched underconditions which remove the exposed trench dielectric material 4 withoutsubstantially etching the underlying contact dielectric material 1.Specific conditions may be selected by those of ordinary skill in theart and may differ depending on the depth of the trench and the natureor composition of the trench (and optionally the contact) dielectriclayer(s). The trench dielectric material 4 may be effectively etchedwithout substantial etching of the underlying contact dielectric layer.The backside of the wafer may be cooled with He at a pressure of 5-20Torr, preferably about 14 Torr. In addition, suitable etching conditionsare as described in co-pending application U.S. Ser. No. 09/326,432 byQiao and Nulty, the relevant portions of which are hereby incorporatedby reference.

[0059] The etching gas may be those typically used by those of ordinaryskill in the art in conventional reactive ion etching. Typically,halocarbons such as CHF₃, C₄F₈, C₂F₆, F-134, F-134a, CF₄, SF₆, NF₃SF₆,Cl₂, HF, HCl, CCl₄, C_(n)H_(x)F_(y) (where n≧1, 2) (see, for example,U.S. Pat. Ser. No. 08/683,407 and/or U.S. Pat. Ser. No. 5,468,342, therelevant portions of which are hereby incorporated by reference) andmixtures thereof, preferably CHF₃, C₄F₈ and/or F-134a and more a mixtureof CHF_(3 and C) ₄F₈ (see U.S. 09/253,991 filed on Feb. 22, 1999) Carbonmonoxide may also be incorporated into the etching gas as an optionalcomponent. Within the context of the present invention, the term“etching gas” refers to the components of the gas or gas mixture whichproduce active components of the plasma which etches the dielecric. Flowrates of etching gases described herein do no include oxygen or carriergases, unless otherwise indicated.

[0060] The total flow rate of etching gas step is typically 5 to 500SCCM, more preferably 15 to 300 SCCM and even more preferably 25 to 250SCCM. Of this flow, up to 450 SCCM, preferably from 4 to 200 SCCM, maycomprise a carrier gas such as Ne, Kr, Xe, CO, CO2, SO2, He, Ar, N2 andmixtures thereof. Typically, the total flow rate of etching gas beforestriking the plasma is about the same or slightly more that the totalflow rate of etching gasw that may be used during an optional flashstrike step or subsequent etch phase(s) or step(s) of the process.Suitable conditions are disclosed in U.S. Ser. Nos. 08/683,407,08/577,751, and/or 08/935,705 and U.S. Pat. Nos. 5,468,342 and/or5,562,801, the relevant portions of which are hereby incorporated byrefernce.

[0061] Under the selected etch conditions for the trench dielectricmaterial an etching rate may be determined, and etching under theselected set of conditions may be conducted for a time sufficient tosubstantially remove trench dielectric layer 4 to a predetermined depth(but at least without etching the contact dielectric material 1). Thedetermination of the conditions and time(s) that provide such an etch iswithin the level of skill of those of ordinary skill in the art, andwill typically take into consideration the thickness and composition ofthe trench dielectric layer and the parameters of the plasma. Suitableetchant gas may comprise C₂H₂F₄, CHF₃, C₄F₈ and CF₄, etchingapproximately 2,000Å of a 3,000 Å thick trech dielectric layer. In oneexample, etching a PSG contact dielectric layer with an etchantcomprising F134 and CHF₃ (C₄F₈ optional) and optionally in the presenceof Ar, at a total pressure of 10-300 mTorr (preferably about 55 mTorr),a magnetic field of 10-50 gauss (preferably about 30 gauss), and at apower 100-2,500 W (preferably from about 500 to about 1,500 W) for alength of time of about 3 minutes, may be sufficient to remobe from8,000 to 9,000 Å of the trench dielectric layer at a rate of 3,000Å/min. The result is trech 6 formed in the trench dielectric layer 4.

[0062] After the trench dielectric material has been etched in a patternenabling formation of an interconnect structure 6, the trenchphotoresist mask 5 may be removed by conventional methods known to thoseof ordinary skill in the art (FIG. 3 and 3B), and a contact opening mask7 may be formed thereon (see FIGS. 4, 4(A), 4(B) and 5). In FIG. 3B, anoptional etch stop layer 15 of silicon nitride is illustrated. Formationof such an etch stop layer is within the level of skill of those ofordinary skill in the art, without undue experimentation. Suitablephotoresist materials for, and methods of forming, the contact openingmask are as described above for the trench mask. The pattern formed inthe contact opening mask is typically a circular pattern, correspondingto the desired shape of the contact. Patterining of the contact openingmask may be performed under suitable conditions known to those ofordinary skill in the art. A BARC layer as described above may also beused to enhance the patterining resolution of the contact hole mask.

[0063] After forming the contact opening mask, the exposed portions ofthe trench dielectric layer and the BARC or inorganic anti-reflectivecoating layer are remove, typically by etching. The trench dielectricmaterial may be etched in the manner described above, and optionally, ina manner that is selective or non-selective with regard to the ARCand/or contact dielectric layer(s). Removal of the ARC layer may beunder similar conditions used to etch an undoped silicate glass, for atotal etch time of about 10 seconds. Non-limiting exemplary etchingconditions for removing the BARC layer comprise exposing the portions ofthe BARC layer to be etched to a plasma comprising CHF₃ and/orCF₄,optionally in the presence of F-134 (preferably a mixture thereof) at apressure of about 5-200 mTorr and a power of 100-1,000 watts in theabsence of Ar. Backside cooling with He at a pressure of 2-30 Torr inthe absence of a magnetic field is preferred.

[0064] A top view of the structure of FIG. 4 is illustrated in FIG. 5,in which the side walls of the trench 6 formed in the trench dielectriclayer 4 are shown, through the hole in the contact mask 7.

[0065] Using the contact opening mask 7, the exposed portion of thetrench dielectric 4 may be removed under conditions as previouslydescribed for the removal of trench dielectric material. This may occurwithout substantial etching of the contact dielectric when the trenchetch is selective for the trench dielectric relative to the contactdielectricf. In one embodiment, at least some of the trench dielectricmaterial below the trench 6 remains over the contact dielectric layer 1.In this embodiment, the contact dielectric layer underlying the trench 6in regions other than those regions being etched is protected frometching by the overlying trench dielectric layer 4 during etching of thecontact opening (the so-called “hard mask” embodiment).

[0066] In this embodiment, the trench dielectric layer 4 may be used asa “hard mask” for forming the contact opening in the contact dielectric,after removing (i.e., in the absence of) the patterned contactphotoresist mask. In this embodiment, the contact mask 7 is used topattern an opening in the trench dielectric layer 4 to expose theregion(s) of the contact dielectric layer overlying the active region ofthe substrate to which the contact opening will be formed, then thecontact mask 7 is removed prior to etching the contact opening throughthe contact dielectric layer 1. After removal of the contact mask layer7, as illustrated in FIG. 6, the semiconductor structure comprises atrench dielectric layer, patterened with a trench 6 and an opening 8 toform a contact opening in the contact dielectric layer 1.

[0067] In the embodiment where the trench dielectric layer 4 comprises apattern or “hard mask” for the contact opening, conditions shouldinclude (a) a trench dielectric thickness which is greater than thetrench thickness (preferably by ≧100 Å, more preferably by ≧200 Å, andeven more preferably by ≧300 Å (typically by about 1,000 Å)) and )b) thecontact dielectric material having a substantially different etch ratethat the trench dielectric material when either material is etched. Inthis context, an etch rate for a first material is “substantiallydifferent” from the etch rate for a second material (alternatively, theetch may be considered “selective” if the ratio of the two etch rates is≧5:1, mmore preferably ≧10:1, even more preferably ≧15:1.

[0068] Prior to etching the contact openings, the trench layer 6 (andoptionally opening 8) may be cleaned by plasma cleaning by aconventional oxygen plasma etch (which may optionally contain CF₄) thenby a conventional sulfuric acid based wet cleaning.

[0069] Conditions for self-aligned contact etching may include one ormore of the conditions listed in Table 1 below: TABLE 1 ConditionGeneral Range Preferred Range RF power (W)   100-1,500 400-600 pressure(mTorr)  10-300 30-80 He cooling pressure (T)  2-30  5-10 C₂H₂F₄ (sccm) 1-50  3-10 CHF₃ (sccm)  0-200 20-50 Ar (sccm)  0-200  50-150 C₄F₈(sccm)  0-50 0-5 Magnetic field (Gauss)  0-50 10-30

[0070] Carbon monoxide may optionally be present.

[0071] Referring to FIG. 7, the contact dielectric layer 1 is etched toform a contact opening 9 to an underlying active region of htesemiconductor substrate adjacent to gate structure 3. During etching ofthe contact opening 9, the patterned trench dielectric layer 4 mayfunction as a “hard mask” for the ocntact dielectric layer 1. Greatertolerance to mask alignment errors during the patterning of opening 8 intrench layer 4 is afforded by self-aligned contact (SAC) techniques.

[0072] Etching the contact dielectric 1 using the trench dielectric 4 asa hard mask may be accomplished under conditions known to those ofordinary skill in the art. Suitable etching conditions are described inco-pending application U.S. Pat. Ser. No. 09/326,432, filed on Jun. 4,1999 by Qiao and Nulty. The etching gas(es), which may be the same as ordifferent from the etching gas(es) for the trench etch step (but whichare preferably selected to provide a selective etch), may be selectedfrom those listed above for the trench etch step, and are selected fromthose that are useful in conventional reactive ion etching.

[0073] In an alternative embodiment, the trench dielectric layer 4 maybe etched to any predetermined depth (but preferably to a depth of fromabout 0.5x to about 1.3x, preferably from about 0.7x to about 1.1x,where x is the thickness of the trench dielectric layer), and during thecontact etch step, the contact opening mask 7 remains over the portionsof the trench and contact dielectric layers not to be etched. When thecontact opening is etched in the presence of the contact opening mask,the contact opeing wall may be formed with a sloped profile (notillustrated in FIG. 6). Suitable etching conditions may be as describedin co-pending application U.S. Pat. Ser. No. 09/326,432 by Qiao andNulty. Alternatively, in this embodiment, the selectivity of etching thetrenching dielectric material relative to the contact dielectricmaterial is not critical, and can be as low as 1:1. The etching gas(es)may be the same as or different from the etching gas(es) described abovefor the trench and/or contact opening etch steps. After etching theopening in the contact dielectric layer 1, the contact opening mask 7may be removed by conventional methods known to those of ordinary skillin the art, the result being illustrated in FIG. 7.

[0074]FIG. 8 illustrates the device after depositing a bulk conductivematerial 11 in the contact opening and trench. Prior to deposition ofthe bulk conductive material 11, an optional liner, wetting and/orbarrier layer 10 may be formed. The layer 10 may promote adherence ofthe conductive material to the dielectric material(s), as well as to amaterial or active region therebelow (e.g., a conductive material suchas tungsten, WSix or Al or doped polysilicon). The layer 10 may also actas a barrier to prevent or inhibit diffusion between the bulk conductivematerial and the underlying substrate. Layer 10 may also comprise asingle layer of material or multiple layers of the same or differentmaterial with independently selected chemical compositions andthicknesses.

[0075] Non-limiting examples of suitable liner/wetting/barrier layermaterial include titaniu, zirconium, hafnium, tantalum, chromium,molybdenum, tungsten, copper, nickel, cobalt, noble metals such asruthenium, rhodium, palladium, osmium, iridium, platinum, gold andsilver, alloys thereof such as titanium-tungsten, aluminum-titanium oraluminum-silicon, and conductive nitrides thereof, such as tantalumnitride and titanium nitride. Preferably the liner/wetting/barrier layeris titanium, a conventional titanium-tungsten alloy or titanium nitride.When the liner/wetting/barrier layer is titanium, deposition of theliner/wetting/barrier layer is preferably followed by rapid thermalannealing (RTA) in an atmosphere comprising N₂ or NH₃.

[0076] The liner/wetting/barrier layer may be depostied by conventionalmethods known to those of ordinary skill in the art such as chemical orplasma vapor deposition, ionized metal plasma, sputtering, etc.Deposition may also be by a collimated process. The thickness of theliner/wetting/barrier layer is typically from about 50 to about 1000 Åthick, preferably from 100 to about 600 Å thick, more preferably from150 to about 500 Å thick. Typically, the thickness is 700 Å as measuredat a flat surface outside the contact. The thickness at the sidewall istypically 0.1 × the flat surface thickness, and the thickness at thebottom to the contact is typically 0.5 × the flat surface thickness.

[0077] While the liner layer may be deposited in an amount sufficient tocover the entire exposed surface of the wafer, within the scope of thepresent invention, it is preferably deposited in an amount sufficient tocover the uppermost surface of the dielectric layer, the side walls andbottom of the opening. During the depositon of the liner/wetting layer,it is preferable that the deposition be conducted in a directionalmanner. Directional deposition may be conducted by conventional methodsknown to those of ordinary skill in the art, for example by collimatedsputtering or by Ion Metal Plasma (IMP) methods. In one embodiment, thecollimation filter may have cells with a 1:1 aspect ratio(height:diameter) or greater.

[0078] A separate barrier layer may be formed in addition to aliner/adhesive layer. When the liner layer is Ti, a separate barrierlayer of TiN or TiW is preferred. Such a barrier layer may be formed bymethods known to those of ordinary skil in the art without undueexperimentation.

[0079] The structures are now prepared for metal deposition with aconductive material, which is not particularly limited and which mayinclude, for example aluminum, tungsten, copper, titanium, alloys andsilicides thereof, etc., preferably aluminum, copper and/or tungsten,more preferably tungsten. Non limiting examples include an Al-0.5% Cualloy, an Al-Si-0.5% Cu alloy, Al°, Al-Ge, Al-Si-Ge, W, Cu and Cualloys. In a preferred embodiment, the conductive material is W.

[0080] Suitable deposition conditions are those known to those ofordinary skill in the art and may comprise depositing a single bulklayer of conductive material. Deposition may be conducted using anotherwise conventional physical vapor deposition apparatus, such as acommercially available sputtering apparatus, such as an ENDURAsputtering system by Applied Materials of Santa Clara, California. Whendepositing a layer of bulk metal (e.g., Al or W), a conventionaltwo-step (cold, then hot) or three-step (cold, hot-slow, then hot-fast)process may be used, where “cold”=T₁, “hot”=T_(2=l , and T) ₁≦T₂−40° C.,preferably T₁≦T₂−60° C. In the first stage deposition, SiH4 is added tothe deposition atmosphere, and nucleation of the conductive materialoccurs. Suitable “three-step” deposition conditions are described inco-pending application U.S. Ser. No. 08/693,978, the relevant portionsof which are hereby incorporated by refernce. The distance from thesputtering target material to the wafer surface is generally from about1′ to about 2″.

[0081] Final processing may comprise planarizing the conductive material11 and optional liner/wetting layer 10, by methods known to those ofordinary skill in the art, such as by chemical-mechanical polishing, theresult being illustrated in FIGS. 9, 10 and 10(B), where FIGS. 10 and10(B) illustrate a top view of the structure illustrated in FIG. 9, FIG.10(B) specifically illustrating misalignment of the contact opening withthe underlying conductive region, which none the less demonstrateseffective formation of SAC metallization. Effective SAC metallizationmay also arise from the semiconductor device illustrated in FIG. 4(B).The conductive material is preferably planarized until its uppermostsurface is substantially coplanar with an uppermost surface of thetrench dielectric layer. Thereafter, the method may further comprisedepositing an interlayer dielectric layer over the (coplanar) conductivematerial and trench dielectric layer by methods known to those skilledin the art. An interlayer dielectric comprising silicon nitride may beused as an interface between layers of a stacked structure (multilayeredstructure) comprising borderless contacts. Although the preferredinterlayer dielectric layer comprises a TEOS layer, any suitabledielectric material from those described above for the trench dielectriclayer may be selected. A low k dielectric may be used, as well assilicon nitride (or etch stop material) for border less contacts. Inaddition a plurality of layers (e.g. BARC, low k, protective) may beused in a multilayer structure. The interlayer dielectric layer, whichmay be from 1000 to 5000 Å thick, may then be planarized by methodsknown to those skilled in the art prior to further processing, forexample by reflowing or chemical mechanical polishing.

[0082] The present invention also relates to an integrated circuitcontaining the above-described structure(s).

[0083] This application describes a method of simultaneously formingmetallization and contact structures in an integrated circuit using atimed-etch procedure. A process for forming metallization and contactstructures in an intgrated circuit comprising an etch stop layer isdescribed in a U.S. Patent Application filed concurrently, entitled“Method of Making Metallization and Contact Structures in an IntegratedCircuit Comprising an Etch Stop Layer” (Applicant's Reference No.PM99026; Attorney Docket No. 7575-0066-77), the entire contents of whichare hereby incorporated by reference.

[0084] The present application describes an etching procedure for makingcontact openings and trench structures through multiple layers ofdielectric materials. The present application describes an etchingprocedure for making contact opening and trench structures throughmultiple layers of dielectric materials. It is within the scope of thepresent invention, to use an analogous method to simultaneously formmetallization and contacts or vias to an underlying metallizationstructure.

[0085] Obviously, numerous modifications and variation of the presentinvention are possible in light of the above teachings. It is thereforeto be understood that within the scope of the appended claims, theinvention may be practiced otherwise than as specifically describedherein.

1. A method for forming metallization and contact structures in anintegrated circuit comprising: a) etching a trench dielectric layer of acomposite structure comprising in sequential order: i) a semiconductorsubstrate comprising an active region, a gate structure thereover, anddielectric spacers adjacent to said gate structure; ii) a contactdielectric layer; and iii) a trench dielectric layer; to form a trenchin said trench dielectric layer under etch conditions which do notsubstantially etch said contact dielectric layer; b) etching saidcontact dielectric layer under conditions which do not substantiallyetch said contact dielectric layer; substantially damage said gatestructure to form a first contact opening that exposes a region of saidsemiconductor substrate and a portion of at least one of said dielectricspacers; and c) depositing a conductive material into said contactopening and said trench.
 2. The method of claim 1, further comprisingforming a second contact opening in said trench dielectric layercorresponding to said first contact opening.
 3. The method of claim 2,wherein during etching said contact dielectric layer, said compositestructure comprises a dielectric contact opening mask.
 4. The method ofclaim 2, wherein during etching said contact dielectric layer, saidcomposite structure further comprises a photoresist material.
 5. Themethod of claim 2, wherein said trench dielectric layer has a thicknessat least 100 A greater than that of said trench.
 6. The mehtod of claim1, wherein etching said contact dielectric layer is conducted underconditions providing an etch rate of at least 5:1 relative to that ofsaid gate structure.
 7. The method of claim 1, further comprisingforming a liner, wetting and/or barrier layer in said first contactopening and said trench.
 8. The mehtod of claim 7, wherein said liner,wetting and/or barrier layer has a thickness of from 50 Å to 1000 Å. 9.The method of claim 1, wherein said liner, wetting and/or barrier layercomprises a material selected from the group consisting of titanium,zirconium, hafnium, tantalum, chromium, molybdenum, tungsten, copper,nickel, cobalt, ruthenium, rhodium, palladium, osmium, iridium,platinum, gold, silver, titanium-tungsten, tantalum nitride and titaniumnitride.
 10. The method of claim 1, wherein said conductive material isselected from the group consisting of tungsten, aluminum, copper andalloys of one of said metals.
 11. The method of claim 1, furhtercomprising removing said conductive material until its uppermost surfaceis substantially coplanar with an uppermost surface of said trenchdielectric layer.
 12. The method of claim 11, further comprisingdepositing an interlayer dielectric layer over said coplanar conductivematerial and said trench dielectric layer.
 13. The method of claim 1,wherein said compostie structure further comprises an anti-reflectivecoating disposed between said trench dielectric layer and said patternedphotoresist.
 14. The method of claim 13, wherein said anti-reflectivecoating comprises an organic anti-reflective coating.
 15. The method ofclaim 13, wherein said anti-reflective coating comprises a dielectricanti-reflective coating.
 16. The method of claim 1, wherein said trenchdielectric layer comprises an undoped silicate glass layer.
 17. Themethod of claim 1, wherein said contact dielectric layer comprises adoped silicate glass.
 18. The method of claim 17, wherein said dopedsilicon oxide contact dielectric layer comprises a member selected fromtthe group consisiting of a phosphosilicate glass, a borophosphosilicateglass and fluorosilicate glass.